Deep Dive
Computer Organization Fundamentals and System Architecture
Computer Organization refers to the internal working and low-level design of how components connect and execute instructions, while Computer Architecture describes what the system provides to programmers at a higher level. A digital computer has five functional units: Input (accepts data and converts to binary), Memory (stores data and instructions in primary RAM/ROM and secondary storage like SSDs), Output (converts binary results to readable format), CPU (containing the ALU for arithmetic/logic and Control Unit for managing operations), and auxiliary units. All units connect through buses — communication pathways that carry data, addresses, and control signals. The address bus runs unidirectional from CPU to memory only, determining how much memory can be addressed using the formula 2^n locations for n-bit address width. The data bus is bidirectional, moving actual data both directions. The control bus is also bidirectional, with the CPU sending commands while devices send back signals like interrupts. Understanding these distinctions is critical for exam success; this topic appears worth 2-7 marks frequently.
Registers, Bus Architectures, and Data Transfer Mechanisms
Registers are the smallest and fastest storage units located inside the CPU, and data cannot access main memory directly — it must first load into registers before operations proceed. Special-purpose registers include the Accumulator (stores results), Program Counter (holds next instruction address), Instruction Register (current instruction), Stack Pointer (top of stack address), Flag Register (operation status like carry and zero), Memory Address Register (for CPU-memory addresses), and Memory Data Register (for CPU-memory data). Single bus architecture uses one common path for all components, reducing cost but creating bottlenecks. Multiple bus architecture uses separate buses, improving speed at higher cost. To prevent data contention when multiple registers try to send simultaneously, multiplexer-based bus systems select only one register at a time using selection lines following the formula log₂(n) for n registers. Tri-state buffers offer an alternative, using three output states — logic 0, logic 1, and high impedance — where a control signal determines output: when C=1, input passes through; when C=0, the circuit opens into high impedance, disconnecting that register from the bus.
Binary Arithmetic, Number Representations, and Overflow
Binary addition follows straightforward rules: 0+0=0 (carry 0), 0+1=1 (carry 0), 1+1=0 (carry 1). CPUs perform subtraction by converting it to addition using Two's complement representation, avoiding costly borrowing circuits. One's complement inverts all bits but creates two zero representations (+0 and -0), introducing hardware complexity. Two's complement performs one's complement then adds 1, producing only one zero and becoming the standard in modern computers. A practical shortcut: copy rightmost bits through the first 1, then invert remaining leftmost bits. For n-bit Two's complement, the range is -2^(n-1) to 2^(n-1)-1. Overflow occurs when results exceed this range, detected by sign inconsistencies — adding two positive numbers and getting a negative result indicates overflow. For example, in 4-bit representation (-2) + (-2) should equal -4, but overflows to positive 6 because the range is only -8 to +7.
Adder Circuits: Half Adder, Full Adder, and Ripple Carry Adder
Addition is the most fundamental arithmetic operation because subtraction, multiplication, and division can all be performed through addition. A Half Adder adds two bits, producing Sum (A XOR B) and Carry (A AND B). Its limitation: it cannot process carry input from previous stages, making it unsuitable for multi-bit addition. A Full Adder overcomes this by accepting three inputs (A, B, and carry-in) and producing Sum = A XOR B XOR Cin and Carry = (A AND B) OR (A XOR B AND Cin). Two Half Adders can be combined into one Full Adder. A Ripple Carry Adder cascades Full Adders in series for multi-bit numbers — the carry output of one becomes the carry input of the next. Example: adding 0110 (6) and 0011 (3) produces 1001 (9). However, RCA has severe speed limitations due to carry propagation delay. If each Full Adder takes 10 nanoseconds, a 4-bit RCA takes 40 nanoseconds, an 8-bit takes 80 nanoseconds, and a 32-bit takes 320 nanoseconds — using the formula n×t where n is bits and t is time per adder.
Carry Lookahead Adder: Solving Carry Propagation Delay
Carry Lookahead Adder solves RCA's speed problem by generating all carries in parallel rather than sequentially. The two key functions are: Generate (Gi = Ai AND Bi) determines when a carry is definitely produced, and Propagate (Pi = Ai XOR Bi) indicates when an incoming carry will propagate. For a 4-bit CLA, the carry equations are: C1 = P0·C0 + G0; C2 = P1·P0·C0 + P1·G0 + G1; C3 = P2·P1·P0·C0 + P2·P1·G0 + P2·G1 + G2; C4 = P3·P2·P1·P0·C0 + P3·P2·P1·G0 + P3·P2·G1 + P3·G2 + G3. These equations are implemented using AND and OR gates configured as a carry generator block. The comparison: RCA is simpler and cheaper but slow; CLA is complex and expensive but fast. RCA generates carries sequentially (one by one); CLA generates them in advance (all at once). RCA is rarely used in modern CPUs; CLA is standard. CLA's complexity pays for itself in speed on high-performance systems.
Booth's Algorithm and ALU Design
Booth's Algorithm performs multiplication of signed binary numbers using Two's complement representation. It uses four registers: M (multiplicand), Q (multiplier), A (accumulator), and Q-1 (extra bit, initially 0). The decision table based on Q0 and Q-1: if both 0 or both 1, perform no operation; if Q0=0 and Q-1=1, compute A=A+M; if Q0=1 and Q-1=0, compute A=A-M. After each operation, perform arithmetic right shift (copying the MSB to preserve sign) and repeat for a number of iterations equal to the number of bits. Example: -5 × +3 in 4-bit representation (range -8 to +7) yields -15; -15 × -16 in 5-bit representation (range -16 to +15) yields 240. The final product appears in the AQ register. The ALU is the computational core, combining three units: Arithmetic (7 operations: transfer, increment, decrement, addition, addition with carry, subtraction, subtraction with borrow), Logic (AND, OR, XOR, NOT), and Shift (left and right). Control signals S2 and S3 select which unit operates (S2S3=00 for arithmetic, 01 for logic, 10 for right shift, 11 for left shift), while S0 and S1 select the specific operation within that unit. The three units connect through a 4×1 multiplexer that routes the correct unit's output as the final ALU output based on control signals.